Senior RTL/SoC Subsystem Verification Engineer

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 35 employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. If you have this type of passion, we invite you to apply for this job.

Job Overview


Senior RTL/SoC Subsystem Verification Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience with UVM verification and UVM environment development.

You will be responsible for RTL SoC/Subsystem verification of ARM based CPUs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows. You will report to the Director of Engineering, Verification.

Key Responsibilities


Project Leadership

  • Help develop test plan definition and development;
  • Micro-architecture design verification, RTL verification, and documentation;
  • Top-level and block-level performance verification, power, and use-case verification; and
  • Support test program development, chip validation, and chip life until production maturity.

Team Management and Building

  • Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

QUALIFICATIONS AND SKILLS


  • 5+ years of experience in UVM verification and UVM environment development;
  • Proficient in testplan definition and testcase development in C/Assembly/SystemVerilog;
  • Expertise in verifying design at RTL level and gate-level simulation;
  • Good understanding of coverage analysis, performance verification and use-case verification;
  • Experience in functional test vector development and post-silicon bring-up/debug;
  • Fluency with scripting languages (e.g., Perl, Python, Shell); and
  • Preferred: knowledge of Power Aware verification is a plus.


ACADEMIC CREDENTIALS


  • BA or MS (preferred) degree in EE/EECS/CS or equivalent.


To apply for this role, please submit your cover letter and resume.