Senior ASIC/SoC Design Engineer

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 35 employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. If you have this type of passion, we invite you to apply for this job.

Job Overview

Senior ASIC/SoC Design Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience with logic design, computer architecture and SoC design. As the ASIC/SoC Design Engineer for Axiado, you will be responsible for all aspects of the SoC design flow. You will work closely with the Architecture, Verification, Physical Design and Software teams, and report to the SVP of Engineering.

Key Responsibilities

Project Leadership

  • Help develop the design and implementation of SoCs;
  • Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
  • Top-level and block-level performance, bandwidth, power, and cost analysis and optimization;
  • Work with FPGA engineers to perform early prototyping; and
  • Support test program development, chip validation, and chip life until production maturity.

Team Management and Building

  • Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.


  • 5+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
  • Proficient in writing clear, implementable micro-architecture specifications;
  • Expertise in writing efficient RTL code in Verilog;
  • Good understanding of assertions, coverage analysis, synthesis, and timing closure;
  • Experience in revision control, regression and bug-tracking tools;
  • Fluency with scripting languages (e.g., Perl, Python);
  • Must have gone through at least one tapeout;
  • Preferred: Lab debug/bring-up experience


  • BA or MS (preferred) degree in EE/EECS/CS or equivalent.

To apply for this role, please submit your cover letter and resume.