Senior ASIC Design Lead Engineer

Job Overview


Axiado is a San José, California-based company that is reshaping the future of cybersecurity for the world. As such, we embrace diversity and equal opportunity in a serious way.

As the Senior ASIC Design Lead Engineer for Axiado, reporting to the SVP of Engineering, you will be responsible for both driving the design and developing the necessary RTL Drive chip-level integration, plan development and verification.

This is an opportunity to join one of the industry’s leading companies in Smart Edge SoCs for IIoT, network/systems control, and management security systems. You should have prior knowledge and experience with high performance digital security processing, especially with ARM or RISC-V intellectual properties.

Key Responsibilities


Project Leadership

  • Help define the processes, methods and tools for design and implementation of SoCs.
  • Supervise the RTL-to-GDS flow and assist with synthesis and timing closure.
  • Algorithm research, micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks.
  • Top level and block level performance; bandwidth, power, and cost analysis and optimization.
  • Support hand-off and integration of blocks into larger SoC environments.
  • Work with FPGA engineers to perform early prototyping.
  • Support test program development, chip validation, and chip life until production maturity.

Team Management and Building

  • Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
  • Coaching and mentoring junior team members.

QUALIFICATIONS AND SKILLS


  • 7+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
  • Hands-on ASIC front-end and back-end design, with experience in CPU design a plus;
  • Proficiency in industry standard front-end EDA tools and methodologies;
  • Strong working knowledge of Verilog/SystemVerilog and C/C++;
  • Experience in Chisel and Scala preferred;
  • Thorough understanding of SoC interconnect protocols;
  • Familiarity with scripting languages (e.g., Tcl, Perl, Python) and flow automation in Linux;
  • Knowledge of embedded software programming and debugging a plus; and
  • BA or MS (preferred) degree in EE/EECS/CS or equivalent.


To apply for this role, please submit your cover letter and resume.