ASIC/SoC Design Engineer II

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 35 employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. If you have this type of passion, we invite you to apply for this job.

Job Overview

ASIC/SoC Design Engineer position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture. As the ASIC/SoC Design Engineer for Axiado, you will have the opportunity to work in all areas of the SoC design flow. You will work closely with the Architecture, Verification, Physical Design and Software teams, and report to the Director of Engineering.

Key Responsibilities


  • Help develop the design and implementation of SoCs;
  • Duties include RTL coding, verification, synthesis, timing closure, and documentation of various RTL blocks;
  • Work with FPGA engineers to perform early prototyping; and
  • Support test program development, chip validation, and chip life until production maturity.


  • Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.


  • 2+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
  • Experience in writing efficient RTL code in Verilog;
  • Knowledge of assertions, coverage analysis, synthesis, and timing closure;
  • Experience in revision control, regression and bug-tracking tools;
  • Fluency with scripting languages (e.g., Perl, Python) and embedded software tools (C, Assembly, trace/debug);
  • Preferred: Lab debug/bring-up experience; and
  • Good writing and verbal communications skills


BA or MS (preferred) degree in EE/EECS/CS or equivalent.


Ottawa, Canada

To apply for this role, please submit your cover letter and resume.